The present invention relates to a semiconductor integrated circuit and specifically to a circuit technique for preventing a malfunction caused due to an off-leak current of a transistor.
SRAM (static random access memory) has been known as a conventional semiconductor integrated circuit. An SRAM includes numerous memory cells. Each memory cell includes, for example, first and second access transistors (N-channel MOS transistors), first and second drive transistors (N-channel MOS transistors), and first and second load transistors (P-channel MOS transistors). The drain of the first drive transistor is connected to one of a pair of bit lines through the first access transistor. The drain of the second drive transistor is connected to the other one of the pair of bit lines through the second access transistor. Each bit line is precharged to a predetermined voltage before read/write cycles.
In recent years, the threshold voltage of the transistor has been decreasing along with the advancement of miniaturization of the semiconductor process. As a result, the influence of the off-leak currents of the access transistors in the SRAM has been significantly increasing. If the total sum of off-leak currents of access transistors of a plurality of memory cells included in the same column (bit line leak current) is increased to be equivalent to an ON-current (drive current) flowing in a drive transistor in a single memory cell which is selected in a read operation in the same column, a desired potential difference cannot be secured between the bit line pair. As a result, there is a possibility that a malfunction occurs in a memory read operation. Further, the off-leak currents of the access transistors change depending on the cell data, temperature, or the like.
In order to solve this problem, K. Agawa et al., “A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM's”, IEEE 2000 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 70–71, discloses a technique wherein the magnitude of the leak current is detected for each bit line in a precharge period of a bit line pair, and in read/write cycles, a compensation current which has the same magnitude as that of the detected bit line leak current is injected to each bit line. However, this conventional technique causes an increase in power consumption due to injection of the compensation current into the bit lines.